Introduction 

The purpose of this document is to provide our customers with a set of guidelines, which will allow products to be both manufacturable and testable. These guidelines are based on industry standard specification.

References 

  • IPC-D-275, Design standard for PCB Fabrication and Assembly.
  • IPC-D300G, Printed Circuit Board Dimensions and Tolerances.
  • IPC-D-325A, Documentation Requirements for PCB Fabrication and Assembly.
  • IPC-SM-782, Surface Mount Design and Land Pattern Standard.
  • IPC-SM-786A, Procedure for handling of Moisture/Reflow sensitive IC’s.
  • IPC-A-610B, Acceptability of Electronic Assemblies.
  • IPC-R-700C, Guidelines for Modification, Rework and Repair of PCA.
  • IPC-4101, Specifications for Base Materials for Printed Circuit Boards.

Workmanship Standards 

All Electronic and Electro-Mechanical assemblies will conform to IPC-A-610 Class 2, Acceptability of Electronic Assemblies.

Documentation Requirements for PCB Assembly. 

  • PCB FABRICATION DRAWING.
  • GERBER FILES: we use gerber files to fabricate printed circuit board and stencils.
  • ASSEMBLY DRAWING, including Engineering Change Orders (ECO).
  • BILL OF MATERIAL.
  • CAD DATA: Centroid data for Pick & Place components, including Reference Designator, Package Description, Part Number, X-Data, Y-Data and Theta Rotation.
  • TEST SPECIFICATIONS, including schematic.

DFM for PCB LAYOUT AND DESIGN

Components 

  1. The land to land spacing for small passive components must be 0.5mm (0.020”).
  2. The land to land spacing for SMT Integrated Circuits must be 1.25mm (0.050”).
  3. The distance between the bodies of two adjacent IC must be 2.5mm (0.100”).
  4. The space between SMT and PTH components must be 2.5mm (0.100”).
  5. All passive components and SOICs shall be parallel to each other and their solder lands perpendicular to the travel direction of the board along the conveyor of the SMT Reflow and Wave solder machine.
  6. Similar types of components should be aligned on the board in the same orientation for ease of component placement, soldering and inspection.
    For ICs pin #1 orientation should be the same.
  7.  Similar component types should be grouped together whenever possible, especially for Memory and Digital logic designs.
  8.  Solder Stencil Design: The openings in the stencil should be the same size as the lands on the board for all components.
  9.  Pin #1 on each IC, and connector to be marked on the layout.
  10. Polarity of LED, Tantalum and Electrolytic Capacitors to be marked on the layout.
  11. Passive components, small standard 0.050” pitch IC’s, low profile components, and low weight components can be placed on the 2nd side of the PC Board.
  12. We recommend LPI Solder mask (Liquid Photo-Imaginable) openings to be 0.003” bigger around the perimeter of any component land solder pads.
  13. PCB Edge Relief: A minimum clearance of 3.0mm (120 mils) is required in the two long edges of the finished panel or PCB to load into the conveyor of the SMT Pick and Place equipment.

Fiducial Marks 

A Fiducial Mark is a printed artwork feature which is created in the same process as the Printed Circuit Board artwork.

The Fiducial Marks provide common measurable points for all steps in the SMT assembly process.

Global Fiducials. Fiducial marks used to locate the position of all circuit feature on an individual board. When a multi image circuit is processed in panel form, the Global Fiducials are referred to as as Panel Fiducials when present for the panel.

  1. AmTECH recommends four global or panel fiducials in the form of a solid filled circle, 1.5mm (0.060”) diameter.
  2. The Global/ panel fiducial shall be located 5.0mm (0.200”) from the edge of the printed circuit board.

Local Fiducials. Fiducial marks used to locate the position of an individual component requiring very precise fine pitch placement.

1. AmTECH recommends two local fiducials for each fine pitch component in the form of a solid filled circle, 1.0mm (0.040”) diameter.

localfiducials1
2. Solder mask clearance requirement for Global/Panel and Local Fiducials.

localfiducials2

Conductors 

Surface Mount conductors width/ clearance GUIDELINES

SMT SMT, QFP QFP, BGA CSP, Flip Chip 

Placement Tolerance
(Pick & Place)

0.075mm – (0.003”)

0.06mm – (0.0024”)

0.05mm – (0.002”)

0.035mm – (0.014”)

Routing Grid

0.4mm – (0.016”)

0.3mm – (0.012”)

0.25mm – (0.010”)

0.2mm – (0.008”)

Conductors/ Clearance

0.2mm – (0.008”)

0.15mm – (0.006”)

0.125mm – (0.005”)

0.1mm – (0.004”)

Lands

0.8mm – 0.032”

0.75mm – 0.030”

0.63mm – 0.025”

0.5mm – 0.020

Drill Hole/Annular Ring

0.4/ 0.2mm

0.35/0.125mm

0.3/ 0.1mm

0.3/ 0.1mm

 

  1. Narrow the surface conductor as it enters the land area to a maximum width of 0.25mm (0.010”). The minimum conductor length should be 0.5mm (0.020”). This neckdown provides an effective solder restriction.
  2. Use a soldermask to prevent the migration of solder away from the component land whenever possible.
  3. Avoid traces between pads on small 0603 and 0402 passive components; they can easily cause tombstone or misalignment.
  4. The option of using smaller geometries for inner layer conductors and clearance normally decrease layer counts and may reduce the overall board thickness and improve the aspect ratio for small drilling.

Via Location Guidelines 

  1. Typical PTH (Plated thru hole) via land diameter at the different PCB layers is about 0.024” diameter pad, drill hole size is 0.014” and finished hole size is about 0.010”.
  2. Via holes shall be located 0.50mm (20 mils) away from the component lands to prevent solder migration of the component land during reflow soldering. Via holes shall be connected with a 0.25mm (0.010”) maximum width surface conductor to the component land.
  3. Tented vias with soldermask or filled vias will also reduce solder migration on assemblies manufactured with a solder reflow process.
  4. If the assembly is to be wave solder, via holes underneath zero clearance components on the primary side should be avoided on boards unless tented with soldermask. (During wave soldering, flux may potentially become trapped under zero clearance devices).
  5. Via holes may also be used as test targets for bed of nails type probes and/or rework ports.
  6. Via holes may be tented if they are not required for node testing or rework.

Panalization dimension and Tooling Hole requirements

Boards or panels that will be moved by automatic handling equipment or pass through automated operations (solder paste printing, Pick & Place component placement, solder reflow, wave solder, cleaning, etc) must have the sides kept free of parts or active circuitry.

    1. Panel borders are required if components are within 3mm (0.120”) of top or bottom board edge and also if the board size is small.
    2. Typically the borders in the panel are 10mm (0.400”) to allow tooling holes to be located at 5mm (0.200”) from both corner edges of the board.

panalization-diagram

  1. For accurate tooling, we prefer four 3.2mm (0.125”) non-plated holes on the corners of the panel or board to provide accurate mechanical registration.
  2. The longer side of the PCB panel should rest on bottom rail.
  3. No thru-hole plating on any of the tooling holes.
  4. No solder mask around any of the tooling holes.
  5. Locate tooling holes 5mm (0.200”) from X and Y corners.

4) V-Score breakout detail 

  1. For de-panalization purposes, ensure components are at least 0.125” away from scored edges.
  2. Typical scoring: 1/3, 1/3, 1/3 of the total thickness of the board.
    A minimum dimension of 0.010” and maximum of 0.020”.
  3. The V-score angle is normally 60 degree.

v-score-breakout-deatail

Download the SMT Guidelines here (pdf)